The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having a bipolar transistor and a field effect transistor and suited for a system of high speed and low power consumption.
A VLSI of high performance having the advantages of both bipolar and MOS can be realized by forming a bipolar transistor and a MOS transistor over a common semiconductor substrate and by composing these transistors in a circuit. This composing technique is called the "Bi-CMOS (Bipolar-CMOS) technique" and can be applied to a VLSI such as a memory or gate array. One representative example of the circuit for realizing the VLSI is shown in FIG. 3. More specifically, FIG. 3 shows one example of the Bi-CMOS inverter circuit, which has its output portion composed of a totem pole of bipolar transistors 120 and 121 and its input portion composed of MOS transistors so that the bipolar transistors of the output portion are driven by the MOS transistors of the input portion.
The features of this circuit of FIG. 3 are as follows Since the input portion is composed of the MOS transistors, the input impedance is very high. Since, moreover, the bipolar transistors of the output portion are complementarily operated by the MOS transistors, no DC current will flow. This serves to minimize the power consumption. Since the output portion is composed of the bipolar transistors, the load driving force is very high. Thus, the Bi-CMOS circuit has a construction suited for VLSI having high speed and the low power consumption.
In the case of this circuit example, the output portion has a totem pole connection which is also used in the well-known TTL (Transistor-Transistor-Logic), and the input portion has a structure of CMOS (Complementary MOS). As understood from this structure, the power source voltage is 5 V like the TTL or CMOS. Not only the example of FIG. 3 but also the Bi-CMOS VLSI such as the memory or gate array being practiced at present is operated at the power source voltage of 5 V.
References concerning such Bi-CMOS techniques are exemplified by many publications such as Japanese Patent Laid-Open Nos. 59-11034, 61-54712 and 60-27227; "0.5 MICRON BICMOS TECHNOLOGY" (1987 IEDM, pp. 838-840); and U.S. Pat. Nos. 4,719,373, 4,661,723, and 4,682,054.
Another circuit is known to aim at high speed and low power consumption by combining bipolar transistors and CMOS transistors, as shown in FIGS. 63 and 64 (as disclosed in Japanese Patent Laid-Open No. 61-84112). This circuit is an inverter which has fundamental operations, as will be described in the following. Common parts are designated by identical reference characters. When an input 308 is at a "0" level, a PMOS field effect transistor (PMOS) 300 is ON to feed the base current to an NPN bipolar transistor (which will hereinafter be referred to as "NPN") 303. Then, the NPN 303 is ON. On the other hand, an NMOS field effect transistor (NMOS) 301 is OFF to feed no base current to an NPN 304 so that the NPN 304 is OFF. As a result, an output 309 assumes a "1" level. On the other hand, if the input 308 assumes the "1" level, the PMOS 300 is OFF to feed no base current to the NPN 303 so that the NPN 303 is OFF. Moreover, the NMOS 301 is ON, and an NMOS 302 having its gate receiving the output level (at "1" at this time) is still ON so that the base current is fed to turn ON the NPN 304. As a result, the output 309 assumes the "0" level. Then, the NMOS 302 is OFF so that the base current to the NPN 304 can be blocked to achieve low power consumption characteristics.
However, the circuit of FIG. 63 has no element for dropping the base potential of the NPN 303 when the output 309 drops, i.e., when the input 308 rises to turn OFF the NPN 303. As a result, the NPN 303 is not promptly turned OFF to establish an ON timing of both the NPN 303 and 304 so that a through current flows from a V.sub.CC power source 180 to a GND power source 181 to obstruct the low power consumption and the high speed.
This point is improved by the arrangement shown in FIG. 64. By providing the NMOS 305, the base voltage of the NPN 303 is abruptly dropped through an NMOS 305, which is turned ON when the input 308 rises, to abruptly turn OFF the NPN 303. An impedance element Z 306 which can be a resistor 307 connected between the base and emitter of the NPN 304 are used to drop the base voltage to the GND potential when the NPN 304 is turned OFF.
Points to be improved in the Bi-CMOS system/circuit technique of the prior art can be summarized into the following two points: one relating to the circuit characteristics (or power consumption) and breakdown voltage at the power source voltage of 5 V; and the other relating to the circuit structure. These two technical problems will be described in the following.
In the prior art, the Bi-CMOS circuit shown in FIG. 3 is typically used with the power source voltage of 5 V. As the improvement in fineness advances, however, problems arise concerning power consumption and the breakdown voltage of the elements. As the structure becomes finer, the number of transistors to be incorporated into one chip will naturally increase. If the power to be consumed by one circuit is assumed to be constant, the power consumption will increase in proportion to the degree of integration. If, at present, the degree of integration is 20,000 gates/chip and the power consumption per chip is 5 W, the power consumption per chip will increase to 10 W as the structure becomes finer so that the integration degree grows to 40,000 gates/chip.
If the power consumption per circuit is constant, as apparent from the above simple calculations, the power consumption per chip will increase in proportion to the inorease in the integration degree accompanying the finer structure. With the increasing power consumption, the temperature in the chip rises to deteriorate the characteristics and reliability of the transistors. Therefore, these transistors have to be cooled. A cooling fan is required in case the power consumption is several watts or less, and water-cooling facilities are required for devices with higher power consumption. These facilities necessary for cooling the chip finally appear as the high cost and large size of the products. This is contrary to the targets such as low cost and small size, which are aimed at by the VLSI technique.
This problem of the increase in the power consumption is becoming more serious as the structure becomes finer and the integration becomes higher. This makes it necessary to reduce the power consumption of the Bi-CMOS circuit. Another problem accompanying the fine structure is the breakdown voltage of the elements. Since the fine structure at present is obtained under a constant power source voltage, the intensity of the electric field to be applied to the elements is increasing on and on to raise a resultant problem of deterioration or dielectric breakdown of the element characteristics.
The second problem concerns the circuit structure. Using the circuit of the prior art, as shown in FIG. 3, it has been found difficult to reduce the power consumption by optimizing the circuit constants while maintaining the high-speed switching characteristics.
First of all, the circuit operations will be briefly described with reference to FIGS. 3 and 4. Let it be assumed that an input voltage signal 162 shown in FIG. 4 is applied to the input 162 of FIG. 3. If the input 162 is first at a High level, a PMOS 100 is OFF, NMOS 110 and 115 are ON, and a NMOS 114 is OFF. If the input changes from High to Low, the PMOS 100 is turned ON whereas the NMOS 115 is turned OFF so that the base current is fed from the PMOS 100 to turn ON a NPN 120. Since the NMOS 110 is turned OFF, on the contrary, a NPN 121 is OFF so that an output 165 becomes High. At this time, the NMOS 114 is turned ON to short-circuit the base and emitter of the bipolar 121 to turn OFF the same without fail.
Next, if the input changes from Low to High, the PMOS 100 is turned OFF, but the NMOS 115 is turned ON to drop the base potential of the bipolar 120 so that the bipolar 120 is turned OFF. On the other hand, the NMOS 110 is turned ON to feed the base current to turn ON the bipolar 121 so that the output 165 becomes Low. At this time, the NMOS 114 is switched from ON to OFF. Immediately after the NMOS 110 becomes ON, the NMOS 114 becomes ON. Since, however, the ON resistance of the NMOS 114 is designed to be higher than that of the NMOS 110, the current from the NMOS 110 is fed not only the NMOS 114 but also to the base of the bipolar 121 to turn ON the bipolar 121.
This circuit is of low power consumption type because the bipolars 120 and 121 have operations complementary to each other. However, the power consumption increases because the through current will flow from the power source 160 to the ground 161 in the transitional state in which the bipolars 120 and 121 are switched. In order to reduce the power consumption, therefore, it is necessary to minimize the through current by switching the bipolars 120 and 121 at a high speed. When the input 162 is changed from Low to High, for example, the bipolar 120 is switched from ON to OFF. In order to speed up this operation, it is necessary to drop the base potential of the bipolar 120 at a high speed by enlarging the channel width W of the NMOS 115 to reduce the ON resistance of the NMOS 115.
In order that this circuit may operate at a high speed when the input is changed from High to Low, on the other hand, it is necessary to feed the base current at a high speed from the PMOS 100 to the bipolar 120. Because of this, it is necessary that the current from the PMOS 100 should not leak to the NMOS 115 but be entirely fed to the base of the bipolar 120. In the transitional state where the input 162 is changed from High to Low, however, the PMOS 100 and NMOS 115 are liable to be simultaneously turned ON so that the current of the PMOS 100 will partially leak to the NMOS 115. In order to reduce this current leakage, therefore, it is necessary to make a design that the channel width W of the NMOS 115 is small to increase the ON resistance of the NMOS 115.
Thus, the prior art circuit shown in FIG. 3 is required, for the purpose of low power consumption, to reduce the through current by designing a large channel width of the NMOS 115 to speed up the bipolar 120 and, for the purpose of high speed, to reduce the leakage current of the base by designing a small channel width for the NMOS 115. In other words, an inconsistency arises if low power consumption and high speed are to be concurrently realized. Therefore, a second object of the present invention is to provide a circuit structure which can simultaneously realize low power consumption and high speed for the circuit by clearing those limits.
In the Bi-CMOS system of low power consumption type realized in accordance with the first main aspect of the present invention, the overhead of the power consumption due to the through current of the circuit cannot be ignored. Therefore, the Bi-CMOS circuit to be used in the low power consumption Bi-CMOS system realized by the first aspect of the invention is suited for use with a second aspect of the invention.
The prior art technique described above takes no special consideration with regard to the connection between the NMOS transistors (NMOS) 301 and 302 for driving the NPN bipolar transistor 304, and encounters the following problems. These problems will be described with reference to FIGS. 65 and 66.
As shown in FIG. 65, a junction capacity 310 for the drain or source of the NMOS is at the node A between the NMOS 301 and 302. A parasitic capacity 311 such as a base capacity or the junction capacity of the NMOS 302 is around the base of the NPN 304. FIG. 66 illustrates the operation timings and the 0N and OFF states of the NMOS 301 and 302, as divided into five regions I to V.
In the region I, the input 308 is set at the "0" level whereas the output 309 is set at the "1" level. At this time, the NMOS 301 is OFF whereas the NMOS 302 is ON so that the potentials at both the point A and the base of the NPN 304 are at the GND potential 181.
In the region II, the input signal 308 begins to rise whereas the output signal 309 begins to drop. At this time, the NMOS 301 and 302 are ON, and the potential at the point A rises with a time constant determined by the ON resistances of the NMOS 301 and 302 and so on. On the other hand, the base potential of the NPN 304 rises and is turned ON.
In the region III, the input 308 is at the "1" level whereas the output 309 is at the "0" level. At this time, the NMOS 301 is ON whereas the NMOS 302 is OFF. The potential at the point A is expressed by V.sub.CC -V.sub.th, if the threshold voltage of the NMOS 301 is designated at V.sub.th. The base potential of the NPN 304 attenuates the time constant of the resistance 307 and parasitic capacity 311 to the GND potential.
In the region IV, the input 308 begins to drop whereas the output 309 begins to rise. At this time, both the NMOS 301 and 302 are OFF to keep the potential of the point A at the state of the region III, and the base potential of the NPN 304 continues to drop with the same time constant as that of the region III.
In the region V, the input 308 is at the "0" level whereas the output 309 is at the "1" level. At this time, the NMOS 301 is OFF whereas the NMOS 302 is ON. The potential of the point A will attenuate toward the GND potential whereas the base potential of the NPN 304 will once rise and then attenuate toward the GND potential. This is caused by the phenomenon that the charges stored in the parasitic capacity 310 are distributed to the parasitic capacity 311 when the NMOS 302 is turned ON. As a result, at the timing when the NPN 303 should be turned ON whereas the NPN 304 should be turned OFF, the NPN 304 is in fact not turned OFF. Therefore, a through current is established from the V.sub.CC power source 180 to the GND power source 181. This through current adversely affects high speed because it increases the power consumption and allows the charge current of the load by the NPN 303 to leak to the NPN 304.
Thus, one of the problems encountered by the technique of the prior art, as shown in FIG. 3, is that the bipolar transistors 120 and 121 are delayed in turning ON because their base potentials fail to reach the base-emitter forward voltage V.sub.BE of the bipolar transistors until the end of the charging operations due to the presence of the parasitic capacity around the bases, although the driver MOS 100 and 110 are turned 0N to feed the base currents of the bipolar transistors.